1. Field of the Invention
The present invention relates generally to synchronous systems and, more particularly, to a technique for shifting the phase of a signal in a synchronous system.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device which is coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. Memory manufacturers provide an array of innovative fast memory chips for various applications. One type of memory device is a standard Synchronous Dynamic Random Access Memory (SDRAM). Synchronous control means that the DRAM latches information from the processor under the control of the system clock. The processor can be told how many clock cycles it takes for the DRAM to complete its task so that the processor can safely implement other tasks while the DRAM is processing its request. In synchronous systems, and especially high speed synchronous systems, the phase of the clock and data may be carefully controlled to insure that data is not overwritten or otherwise lost as it is clocked through the system.
Because microprocessor technology enables current microprocessors to operate faster than current memory devices, techniques for increasing the speed of memory devices are often implemented. One technique for increasing the speed of a SDRAM is called a xe2x80x9cprefetch.xe2x80x9d In a prefetch system, more than one data word is fetched from the memory on each address cycle. The data may be temporarily stored in a buffer. Multiple words of data can then be sequentially clocked out for each address access. The main advantage of this approach is that for any given technology data can be accessed in multiples of the internal clock rate of the DRAM.
In a Double Data Rate (DDR) memory, the data transfer rate is twice that of a regular SDRAM because the DDR""s I/O data can be strobed twice for every clock cycle. Thus, data is sent on both the rising and falling edge of the clock signal rather than just the rising edge of the clock signal as in typical Single Data Rate (SDR) systems. With the increased rate of data transfer in synchronous systems such as DDR systems, matching the clock and data rates becomes more difficult. If the data and clock signals between the controller and memory are out of phase, it may be beneficial to shift the phase of the data or clock to optimize the likelihood of clocking of the data without losing any of the information.
The present invention may address one or more of the problems set forth above.